Previous methods for fabricating JFET's in the same silicon integrated circuit process with NPN transistors have used an N-type epitaxial layer as the N channel region where P+ base regions acted as the gate and N+ contacts as the source and drain regions.
This approach pays a penalty in device size and performance as the N-type epitaxial layer with its large tolerance in thickness and resistivity, dominated the JFET characteristics.
M. N. Phan, et al, "A Fast 1024-Bit Bipolar RAM Using JFET Load Devices", 1977 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp. 70-71 and 238 discloses the formation of an N-epitaxial layer on top of a P-type substrate, through which a recessed oxidation isolation is formed which goes through the epitaxial layer and into the substrate. The process of oxidation at the epitaxial layer/substrate interface depletes the substrate surface of the boron P-type dopant, thereby forming an N-type channel along the bottom of the recessed oxide, which becomes the channel of the JFET. This JFET process, which is compatible with a bipolar process, contributes no control over the transconductance characteristics of the JFET device. Furthermore, the JFET device cannot be used as a switch since the entire epitaxial layer itself is the gate for the device and cannot be switched at a rapid enough rate to enable its use as a practical logical element.
B. Jayant Baliga, et al., "Gambi: Gate Modulated Bipolar Transistor", Solid State Electronics, 1975, Vol. 18, pp. 937-941, discloses a merged JFET device and bipolar transistor which merges the collector of the PNP transistor with the gate of the JFET. By reverse biasing the base/collector junction, the base current is pinched off in JFET fashion, using the N-type epitaxial layer as the channel. The JFET device is subject to the variability in the epitaxial layer thickness and doping levels which yields a JFET device having broad tolerances in the transconductance. The device can only be used as a bistable device and never as an active logic switch.
The device makes poor use of silicon area and has a different structure than that disclosed in the subject disclosures.